Epson ARM.POWERED ARM720T Manual de usuario

ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU MANUALEPSON Electronic Devices WebsiteELECTRONIC DEVICES MARKETING DIVISIONhttp://www.eps

CONTENTSvi EPSON ARM720T CORE CPU MANUALList of TablesTable 1-1 Key to tables ...

7: Memory Management Unit7-4 EPSON ARM720T CORE CPU MANUAL7.3 Address translationThe MMU translates VAs generated by the CPU core, and by CP15 registe

7: Memory Management UnitARM720T CORE CPU MANUAL EPSON 7-5The translation table has up to 4096 x 32-bit entries, each describing 1MB of virtual memory

7: Memory Management Unit7-6 EPSON ARM720T CORE CPU MANUAL7.3.2 Level one fetchBits [31:14] of the Translation Table Base Register are concatenated wi

7: Memory Management UnitARM720T CORE CPU MANUAL EPSON 7-7Level one descriptor bit assignments are shown in Table 7-2. The two least significant bits

7: Memory Management Unit7-8 EPSON ARM720T CORE CPU MANUAL7.3.4 Section descriptorA section descriptor provides the base address of a 1MB block of mem

7: Memory Management UnitARM720T CORE CPU MANUAL EPSON 7-9Coarse page table descriptor bit assignments are described in Table 7-5.7.3.6 Fine page tabl

7: Memory Management Unit7-10 EPSON ARM720T CORE CPU MANUAL7.3.7 Translating section referencesFigure 7-8 shows the complete section translation seque

7: Memory Management UnitARM720T CORE CPU MANUAL EPSON 7-11A level two descriptor defines a tiny, a small, or a large page descriptor, or is invalid:•

7: Memory Management Unit7-12 EPSON ARM720T CORE CPU MANUAL7.3.9 Translating large page referencesFigure 7-10 shows the complete translation sequence

7: Memory Management UnitARM720T CORE CPU MANUAL EPSON 7-137.3.10 Translating small page referencesFigure 7-11 shows the complete translation sequence

CONTENTSARM720T CORE CPU MANUAL EPSON viiTable 9-7 Determining the cause of entry to debug state ...

7: Memory Management Unit7-14 EPSON ARM720T CORE CPU MANUAL7.3.11 Translating tiny page referencesFigure 7-12 shows the complete translation sequence

7: Memory Management UnitARM720T CORE CPU MANUAL EPSON 7-157.4 MMU faults and CPU abortsThe MMU generates an abort on the following types of faults:•

7: Memory Management Unit7-16 EPSON ARM720T CORE CPU MANUAL7.5 Fault address and fault status registersOn an abort, the MMU places an encoded 4-bit va

7: Memory Management UnitARM720T CORE CPU MANUAL EPSON 7-177.6 Domain access controlMMU accesses are primarily controlled through the use of domains.

7: Memory Management Unit7-18 EPSON ARM720T CORE CPU MANUALTable 7-10 shows how to interpret the Access Permission (AP) bits and how their interpretat

7: Memory Management UnitARM720T CORE CPU MANUAL EPSON 7-197.7 Fault checking sequenceThe sequence the MMU uses to check for access faults is differen

7: Memory Management Unit7-20 EPSON ARM720T CORE CPU MANUAL7.7.2 Translation fault There are two types of translation fault:Section A section transla

7: Memory Management UnitARM720T CORE CPU MANUAL EPSON 7-217.8 External abortsIn addition to the MMU-generated aborts, the ARM720T processor can be ex

7: Memory Management Unit7-22 EPSON ARM720T CORE CPU MANUALTHIS PAGE IS BLANK.

8Coprocessor Interface

CONTENTSviii EPSON ARM DDI 0229BTHIS PAGE IS BLANK.

8: Coprocessor InterfaceARM720T CORE CPU MANUAL EPSON 8-18 Coprocessor InterfaceThis chapter describes the coprocessor interface on the ARM720T proces

8: Coprocessor Interface8-2 EPSON ARM720T CORE CPU MANUALThe coprocessor: 1 Decodes instructions to determine whether it can accept the instruction.2

8: Coprocessor InterfaceARM720T CORE CPU MANUAL EPSON 8-38.2 Coprocessor interface signalsThe signals used to interface the ARM720T core to a coproces

8: Coprocessor Interface8-4 EPSON ARM720T CORE CPU MANUAL8.3 Pipeline-following signalsEvery coprocessor in the system must contain a pipeline followe

8: Coprocessor InterfaceARM720T CORE CPU MANUAL EPSON 8-58.4 Coprocessor interface handshakingThe ARM720T core and any coprocessors in the system perf

8: Coprocessor Interface8-6 EPSON ARM720T CORE CPU MANUAL8.4.3 Coprocessor signalingThe coprocessor signals as follows:Coprocessor absentIf a coproces

8: Coprocessor InterfaceARM720T CORE CPU MANUAL EPSON 8-78.4.5 Coprocessor register transfer instructionsThe coprocessor register transfer instruction

8: Coprocessor Interface8-8 EPSON ARM720T CORE CPU MANUAL8.4.7 Coprocessor load and store operationsThe coprocessor load and store instructions, LDC a

8: Coprocessor InterfaceARM720T CORE CPU MANUAL EPSON 8-98.5 Connecting coprocessorsA coprocessor in a system based on an ARM720T processor must have

Preface

8: Coprocessor Interface8-10 EPSON ARM720T CORE CPU MANUAL8.6 Not using an external coprocessor If you are implementing a system that does not include

9Debugging Your System

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-19 Debugging Your SystemThis chapter describes how to debug a system based on an ARM720T proce

9: Debugging Your System9-2 EPSON ARM720T CORE CPU MANUAL9.1 About debugging your systemThe advanced debugging features of the ARM720T processor make

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-39.2 Controlling debuggingThe major blocks of the ARM720T processor are:ARM CPU core This has

9: Debugging Your System9-4 EPSON ARM720T CORE CPU MANUAL9.2.1 Debug modesYou can perform debugging in either of the following modes:Halt mode When t

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-59.3 Entry into debug stateIf the system is in halt mode, any of the following types of interr

9: Debugging Your System9-6 EPSON ARM720T CORE CPU MANUAL9.3.1 Entry into debug state on breakpointThe ARM720T processor marks instructions as being b

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-79.3.3 Entry into debug state on debug requestAn ARM720T core in halt mode can be forced into

9: Debugging Your System9-8 EPSON ARM720T CORE CPU MANUAL9.3.5 ClocksThe system and test clocks must be synchronized externally to the processor. The

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-99.4 Debug interfaceThe ARM720T processor debug interface is based on IEEE Std. 1149.1- 1990,

9: Debugging Your System9-10 EPSON ARM720T CORE CPU MANUAL9.6 The EmbeddedICE-RT macrocellThe ARM720T processor EmbeddedICE-RT macrocell module provid

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-11Abort status register This register identifies whether an abort exception entry was caused b

9: Debugging Your System9-12 EPSON ARM720T CORE CPU MANUAL9.8 EmbeddedICE-RT register mapThe locations of the EmbeddedICE-RT registers are shown in Ta

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-139.9.2 Restrictions on monitor-mode debuggingThere are several restrictions you must be aware

9: Debugging Your System9-14 EPSON ARM720T CORE CPU MANUAL9.10 The debug communications channelThe ARM720T EmbeddedICE-RT macrocell contains a Debug C

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-15The Domain Access Control Register bit assignments are shown in Table 9-2. Note: If executio

9: Debugging Your System9-16 EPSON ARM720T CORE CPU MANUAL9.10.2 Communications through the DCCMessages can be sent and received through the DCC.Sendi

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-179.11 Scan chains and the JTAG interfaceThere are three JTAG-style scan chains within the ARM

PrefaceARM720T CORE CPU MANUAL EPSON xiPrefaceThis preface introduces the ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU Manual. It cont

9: Debugging Your System9-18 EPSON ARM720T CORE CPU MANUALScan chain 15Scan chain 15 is dedicated to the system control coprocessor registers (the CP1

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-199.12 The TAP controllerThe TAP controller is a state machine that determines the state of th

9: Debugging Your System9-20 EPSON ARM720T CORE CPU MANUAL9.13 Public JTAG instructionsTable 9-4 shows the public JTAG instructions.In the following d

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-219.13.3 IDCODE (b1110)The IDCODE instruction connects the device identification code register

9: Debugging Your System9-22 EPSON ARM720T CORE CPU MANUAL9.14 Test data registersThe six test data registers that can connect between DBGTDI and DBGT

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-239.14.3 Instruction registerPurpose Changes the current TAP instruction.Length 4 bits.Operati

9: Debugging Your System9-24 EPSON ARM720T CORE CPU MANUAL9.14.5 Scan chains 1 and 2The scan chains enable serial access to the core logic, and to the

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-25During SHIFT-DR, a data value is shifted into the serial register. Bits 32 to 36 specify the

9: Debugging Your System9-26 EPSON ARM720T CORE CPU MANUAL9.16 Examining the core and the system in debug stateWhen the ARM720T processor is in debug

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-279.16.1 Determining the core stateWhen the processor has entered debug state from Thumb state

Prefacexii EPSON ARM720T CORE CPU MANUALChapter 8 Coprocessor Interface Read this chapter for a description on how to connect coprocessors to the ARM1

9: Debugging Your System9-28 EPSON ARM720T CORE CPU MANUALAll these instructions execute at debug speed. Debug speed is much slower than system speed.

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-29When the ARM720T processor returns to debug state after a system speed access, bit 33 of sca

9: Debugging Your System9-30 EPSON ARM720T CORE CPU MANUALFigure 9-3 on page 9-5 shows that the final memory access occurs in the cycle after DBGACK g

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-319.18.3 Watchpoint with another exceptionIf a watchpointed access simultaneously causes a Dat

9: Debugging Your System9-32 EPSON ARM720T CORE CPU MANUAL9.18.6 Summary of return address calculationsTo determine whether entry to debug state was d

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-339.19.2 InterruptsWhen the ARM720T processor enters debug state, interrupts are automatically

9: Debugging Your System9-34 EPSON ARM720T CORE CPU MANUALFigure 9-12 EmbeddedICE-RT block diagramThe data to be written is shifted into the 32-bit d

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-359.20.2 Using the data, and address mask registersFor each value register in a register pair,

9: Debugging Your System9-36 EPSON ARM720T CORE CPU MANUALDBGEXT[1:0] Is an external input to EmbeddedICE-RT logic that enables the watchpoint to be d

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-373 Program the data value register only when you require a data-dependent breakpoint, that is

PrefaceARM720T CORE CPU MANUAL EPSON xiiiTiming diagram conventionsThis manual contains one or more timing diagrams. The following key explains the co

9: Debugging Your System9-38 EPSON ARM720T CORE CPU MANUAL9.22 Programming watchpointsThis section contains examples of how to program the watchpoint

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-399.24 Debug control registerThe Debug Control Register is six bits wide. Writes to the Debug

9: Debugging Your System9-40 EPSON ARM720T CORE CPU MANUAL9.24.1 Disabling interruptsIRQs and FIQs are disabled under the following conditions:• durin

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-419.25 Debug status registerThe debug status register is 13 bits wide. If it is accessed for a

9: Debugging Your System9-42 EPSON ARM720T CORE CPU MANUALThe structure of the debug control and status registers is shown in Figure 9-17.Figure 9-17

9: Debugging Your SystemARM720T CORE CPU MANUAL EPSON 9-439.26 Coupling breakpoints and watchpointsYou can couple watchpoint units 1 and 0 together us

9: Debugging Your System9-44 EPSON ARM720T CORE CPU MANUAL9.26.2 DBGRNG signalThe DBGRNG signal is derived as follows:DBGRNG = ((({Av[31:0],Cv[4:0]} X

10ETM Interface

10: ETM InterfaceARM720T CORE CPU MANUAL EPSON 10-110 ETM InterfaceThis chapter describes the ETM interface that is provided on the ARM720T processor.

Prefacexiv EPSON ARM720T CORE CPU MANUALTHIS PAGE IS BLANK.

10: ETM Interface10-2 EPSON ARM720T CORE CPU MANUAL10.3 Connections between the ETM7 macrocell and the ARM720T processorTable 10-1 shows the connectio

10: ETM InterfaceARM720T CORE CPU MANUAL EPSON 10-310.4 Clocks and resetsThe ARM720T processor uses a single clock, HCLK, as both the main system cloc

10: ETM Interface10-4 EPSON ARM720T CORE CPU MANUALTHIS PAGE IS BLANK.

11Test Support

11: Test SupportARM720T CORE CPU MANUAL EPSON 11-111 Test SupportThis chapter describes the test methodology and the CP15 test registers for the ARM72

11: Test Support11-2 EPSON ARM720T CORE CPU MANUAL11.2 Automatic Test Pattern Generation (ATPG)Scan insertion is already performed and fixed for the A

11: Test SupportARM720T CORE CPU MANUAL EPSON 11-311.3 Test State RegisterThe test state register contains only one bit, bit 0:Bit 0 set Enable MMU a

11: Test Support11-4 EPSON ARM720T CORE CPU MANUALTable 11-3 summarizes register c7, c9, and c15 operations.The CAM read format for Rd is shown in Fig

11: Test SupportARM720T CORE CPU MANUAL EPSON 11-5The RAM read format for Rd is shown in Figure 11-4.Figure 11-4 Rd format, RAM readThe RAM write for

1Introduction

11: Test Support11-6 EPSON ARM720T CORE CPU MANUALThe CAM match, RAM read format for data is shown in Figure 11-9.Figure 11-9 Data format, CAM match

11: Test SupportARM720T CORE CPU MANUAL EPSON 11-7Example 11-1 shows sample code for performing software test of the cache. It contains typical operat

11: Test Support11-8 EPSON ARM720T CORE CPU MANUAL; Now read and checkMOV r8,#8MOV r2,#0x10MOV r1,#0loop1 MCR p15,3,r1,c15,c3,0 ; write C15.C to ‘0’MC

11: Test SupportARM720T CORE CPU MANUAL EPSON 11-9The CP15 register c15 operations that operate on the CAM, RAM1, and RAM2 are shown in Table 11-5. No

11: Test Support11-10 EPSON ARM720T CORE CPU MANUALFigure 11-12 shows the format of Rd for CAM writes and data for CAM reads.Figure 11-12 Rd format,

11: Test SupportARM720T CORE CPU MANUAL EPSON 11-11In Figure 11-13, AP[3:0] determines the setting of the access permission bits for a memory region.

11: Test Support11-12 EPSON ARM720T CORE CPU MANUALIn Figure 11-15, SIZE_R2 sets the memory region size. The allowed values of SIZE_R2 are shown in Ta

11: Test SupportARM720T CORE CPU MANUAL EPSON 11-13Example 11-2 shows sample code for performing software test of the MMU. It contains typical operati

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Appendix ASignal Descriptions

NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permis-sion of Seiko Epson. Seiko Eps

A: Signal DescriptionsARM720T CORE CPU MANUAL EPSON A-1A Signal DescriptionsThis chapter describes the interface signals of the ARM720T processor. It

A: Signal DescriptionsA-2 EPSON ARM720T CORE CPU MANUALA.2 Coprocessor interface signals The coprocessor interface signals are shown in Table A-2.Tabl

A: Signal DescriptionsARM720T CORE CPU MANUAL EPSON A-3A.3 JTAG and test signalsJTAG and test signal descriptions are shown in Table A-3.Table A-3 JT

A: Signal DescriptionsA-4 EPSON ARM720T CORE CPU MANUALA.4 Debugger signalsThe debugger signal descriptions are shown in Table A-4.DBGTDO Output Test

A: Signal DescriptionsARM720T CORE CPU MANUAL EPSON A-5A.5 Embedded trace macrocell interface signalsThe ETM interface signals are shown in Table A-5.

A: Signal DescriptionsA-6 EPSON ARM720T CORE CPU MANUALETMTBIT Output Thumb state.This signal, when HIGH, indicates that the processor is executing th

A: Signal DescriptionsARM720T CORE CPU MANUAL EPSON A-7A.6 ATPG test signalsATPG test signals used by the ARM720T processor are shown in Table A-6. A.

A: Signal DescriptionsA-8 EPSON ARM720T CORE CPU MANUALTHIS PAGE IS BLANK.

Glossary

1: IntroductionARM720T CORE CPU MANUAL EPSON 1-11 IntroductionThis chapter provides an introduction to the ARM720T processor. It contains the followin

GlossaryARM720T CORE CPU MANUAL EPSON Glossary-1GlossaryThis glossary describes some of the terms used in this manual. Where terms can have several me

GlossaryGlossary-2 EPSON ARM720T CORE CPU MANUALComplex Instruction Set Computer A microprocessor that recognizes a large number of instructions.See a

GlossaryARM720T CORE CPU MANUAL EPSON Glossary-3Halt mode One of two debugging modes. When debugging is performed in halt mode, the core stops when i

GlossaryGlossary-4 EPSON ARM720T CORE CPU MANUALMonitor mode One of two debugging modes. When debugging is performed in monitor mode, the core does n

GlossaryARM720T CORE CPU MANUAL EPSON Glossary-5Saved Program Status Register The Saved Program Status Register which is associated with the current p

GlossaryGlossary-6 EPSON ARM720T CORE CPU MANUALTest Access Port The collection of four mandatory and one optional terminals that form the input/outpu

Index

IndexARM DDI 0229B EPSON Index-1IndexThe items in this index are listed in alphabetical order, with symbols and numerics appearing at the end. The ref

1: Introduction1-2 EPSON ARM720T CORE CPU MANUALA block diagram of the ARM720T processor is shown in Figure 1-1.Figure 1-1 720T Block diagramMMUData

Index Index-2 EPSON ARM DDI 0229Blevel two 7-10section 7-8Device identification code 9-21, 9-22Disabling EmbeddedICE-RT 9-11Disabling the ETM interfac

IndexARM DDI 0229B EPSON Index-3test registers 11-8Modes, privileged 8-10Monitor mode 9-4, 9-12, 9-13Multi-ICE 9-8OOperating modesAbort mode 2-4changi

Index Index-4 EPSON ARM DDI 0229BSWI 2-13System mode 2-4System speedinstruction 9-28, 9-31System statedetermining 9-28TT bit (in CPSR) 2-8TAPcontrolle

International Sales Operations AMERICA EPSON ELECTRONICS AMERICA, INC.- HEADQUARTERS - 150 River Oaks ParkwaySan Jose, CA 95134, U.S.A.Phone: +1-408

ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU MANUALEPSON Electronic Devices WebsiteELECTRONIC DEVICES MARKETING DIVISIONhttp://www.eps

1: IntroductionARM720T CORE CPU MANUAL EPSON 1-3The functional signals on the ARM720T processor are shown in Figure 1-2.Figure 1-2 ARM720T processor

1: Introduction1-4 EPSON ARM720T CORE CPU MANUALChanges to the programmer’s modelTo provide support for the EmbeddedICE-RT macrocell, the following ch

1: IntroductionARM720T CORE CPU MANUAL EPSON 1-51.2 CoprocessorsThe ARM720T processor has an internal coprocessor designated CP15 for internal control

1: Introduction1-6 EPSON ARM720T CORE CPU MANUAL1.3.1 Format summaryThis section provides a summary of the ARM and Thumb instruction sets:•ARM instruc

1: IntroductionARM720T CORE CPU MANUAL EPSON 1-71.3.2 ARM instruction setThis section gives an overview of the ARM instructions available. For full de

1: Introduction1-8 EPSON ARM720T CORE CPU MANUALThe ARM instruction set summary is shown in Table 1-2.Table 1-2 ARM instruction summaryOperation Asse

1: IntroductionARM720T CORE CPU MANUAL EPSON 1-9Load Word LDR{cond} <Rd>, <a_mode2>Word with User Mode privilege LDR{cond}T <Rd>, &l

Preface1 Introduction2 Programmer’s Model3 Configuration4 Instruction and Data Cache5Write Buffer6 The Bus Interface7 Memory Management Unit8 Coproces

1: Introduction1-10 EPSON ARM720T CORE CPU MANUALAddressing mode 2, <a_mode2>, is shown in Table 1-3.Coprocessors Data operations CDP{cond} p<

1: IntroductionARM720T CORE CPU MANUAL EPSON 1-11Addressing mode 2 (privileged), <a_mode2P>, is shown in Table 1-4.Addressing mode 3 (signed byt

1: Introduction1-12 EPSON ARM720T CORE CPU MANUALAddressing mode 4 (store), <a_mode4S>, is shown in Table 1-7.Addressing mode 5 (coprocessor dat

1: IntroductionARM720T CORE CPU MANUAL EPSON 1-13Condition fields, {cond}, are shown in Table 1-11.Table 1-11 Condition fieldsSuffix Description Cond

1: Introduction1-14 EPSON ARM720T CORE CPU MANUAL1.3.3 Thumb instruction setThis section gives an overview of the Thumb instructions available. For fu

1: IntroductionARM720T CORE CPU MANUAL EPSON 1-15The Thumb instruction set summary is shown in Table 1-12.Table 1-12 Thumb instruction summaryOperati

1: Introduction1-16 EPSON ARM720T CORE CPU MANUALShift/Rotate Logical shift left LSL <Rd>, <Rs>, #<5bit_shift_imm> LSL <Rd>, &

1: IntroductionARM720T CORE CPU MANUAL EPSON 1-17 Note: All thumb fetches are done as 32-bit bus transactions using the 32-bit thumb prefetch buffer.L

1: Introduction1-18 EPSON ARM720T CORE CPU MANUAL1.4 Silicon revisionsThis manual is for revision r4p2 of the ARM720T macrocell. See Product revision

2Programmer’s Model

2: Programmer’s ModelARM720T CORE CPU MANUAL EPSON 2-12 Programmer’s ModelThis chapter describes the programmer’s model for the ARM720T processor. It

2: Programmer’s Model2-2 EPSON ARM720T CORE CPU MANUAL2.2 Memory formatsThe ARM720T processor views memory as a linear collection of bytes numbered up

2: Programmer’s ModelARM720T CORE CPU MANUAL EPSON 2-32.2.2 Little-endian formatIn little-endian format, the lowest numbered byte in a word is conside

2: Programmer’s Model2-4 EPSON ARM720T CORE CPU MANUAL2.5 Operating modesThe ARM720T processor supports seven modes of operation, as shown in Table 2-

2: Programmer’s ModelARM720T CORE CPU MANUAL EPSON 2-5Interrupt modesFIQ mode has seven banked registers mapped to r8-14 (r8_fiq-r14_fiq). In ARM stat

2: Programmer’s Model2-6 EPSON ARM720T CORE CPU MANUAL2.6.2 The Thumb state register setThe Thumb state register set is a subset of the ARM state set.

2: Programmer’s ModelARM720T CORE CPU MANUAL EPSON 2-72.6.3 The relationship between ARM and Thumb state registers The Thumb state registers relate to

2: Programmer’s Model2-8 EPSON ARM720T CORE CPU MANUAL2.7 Program status registers The ARM720T processor contains a CPSR, and five SPSRs for use by ex

2: Programmer’s ModelARM720T CORE CPU MANUAL EPSON 2-92.7.3 Reserved bits The remaining bits in the PSRs are reserved. When changing flag or control b

CONTENTSARM720T CORE CPU MANUAL EPSON iContentsPrefaceAbout this document...

2: Programmer’s Model2-10 EPSON ARM720T CORE CPU MANUAL2.8 ExceptionsExceptions arise whenever the normal flow of a program has to be halted temporari

2: Programmer’s ModelARM720T CORE CPU MANUAL EPSON 2-112.8.2 Action on leaving an exception On completion, the exception handler:1 Moves the LR, minus

2: Programmer’s Model2-12 EPSON ARM720T CORE CPU MANUAL2.8.4 Fast interrupt requestThe FIQ exception is used for most performance-critical interrupts

2: Programmer’s ModelARM720T CORE CPU MANUAL EPSON 2-13After fixing the reason for the abort, the handler must execute the following irrespective of t

2: Programmer’s Model2-14 EPSON ARM720T CORE CPU MANUAL2.8.10 Exception prioritiesWhen multiple exceptions arise at the same time, a fixed priority sy

2: Programmer’s ModelARM720T CORE CPU MANUAL EPSON 2-152.9 Relocation of low virtual addresses by the FCSE PIDThe ARM720T processor provides a mechani

2: Programmer’s Model2-16 EPSON ARM720T CORE CPU MANUAL2.10 ResetWhen the HRESETn signal goes LOW, the ARM720T processor:1 Abandons the executing inst

2: Programmer’s ModelARM720T CORE CPU MANUAL EPSON 2-172.11 Implementation-defined behavior of instructionsThe ARM Architecture Reference Manual defin

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3Configuration

CONTENTSii EPSON ARM720T CORE CPU MANUAL6.9 Reset ...

3: ConfigurationARM720T CORE CPU MANUAL EPSON 3-13 ConfigurationThis chapter describes the configuration of the ARM720T processor. It contains the fol

3: Configuration3-2 EPSON ARM720T CORE CPU MANUAL3.2 Internal coprocessor instructionsThe instruction set for the ARM720T processor enables you to imp

3: ConfigurationARM720T CORE CPU MANUAL EPSON 3-33.3 RegistersThe ARM720T processor contains registers that control the cache and MMU operation. You c

3: Configuration3-4 EPSON ARM720T CORE CPU MANUAL3.3.2 Control RegisterReading from CP15 Register 1 reads the control bits. The CRm and opcode_2 field

3: ConfigurationARM720T CORE CPU MANUAL EPSON 3-5Bits 12:10 When read, this returns an Unpredictable value. When written, it Should Be Zero, or a val

3: Configuration3-6 EPSON ARM720T CORE CPU MANUAL3.3.4 Domain Access Control RegisterReading from CP15 Register 3 returns the value of the Domain Acce

3: ConfigurationARM720T CORE CPU MANUAL EPSON 3-73.3.6 Fault Address Register Reading CP15 Register 6 returns the value of the Fault Address Register

3: Configuration3-8 EPSON ARM720T CORE CPU MANUALIn the instructions shown in Table 3-3, c7 is the preferred value for the CRn field, because it indic

3: ConfigurationARM720T CORE CPU MANUAL EPSON 3-93.3.10 Register 14, reservedAccessing this register is undefined. Writing to Register 14 is Undefined

CONTENTSARM720T CORE CPU MANUAL EPSON iii10 ETM Interface10.1 About the ETM interface...

3: Configuration3-10 EPSON ARM720T CORE CPU MANUALTHIS PAGE IS BLANK.

4Instruction and Data Cache

4: Instruction and Data CacheARM720T CORE CPU MANUAL EPSON 4-14 Instruction and Data CacheThis chapter describes the instruction and data cache. It co

4: Instruction and Data Cache4-2 EPSON ARM720T CORE CPU MANUAL4.1.3 Read-lock-writeThe IDC treats the read-lock-write instruction as a special case:Re

5Write Buffer

5: Write BufferARM720T CORE CPU MANUAL EPSON 5-15 Write BufferThis chapter describes the write buffer. It contains the following sections:5.1 About th

5: Write Buffer5-2 EPSON ARM720T CORE CPU MANUAL5.2 Write buffer operationYou control the operation of the write buffer with CP15 register 1, the Cont

6The Bus Interface

CONTENTSiv EPSON ARM720T CORE CPU MANUALList of FiguresFigure 1-1 720T Block diagram ...

6: The Bus InterfaceARM720T CORE CPU MANUAL EPSON 6-16 The Bus InterfaceThis chapter describes the signals on the bus interface of the ARM720T process

6: The Bus Interface6-2 EPSON ARM720T CORE CPU MANUALFigure 6-1 shows a transfer with no wait states (this is the simplest type of transfer). Figure 6

6: The Bus InterfaceARM720T CORE CPU MANUAL EPSON 6-36.2 Bus interface signalsThe signals in the ARM720T processor bus interface can be grouped into t

6: The Bus Interface6-4 EPSON ARM720T CORE CPU MANUALThe AHB bus master interface signals are shown in Figure 6-2.Figure 6-2 AHB bus master interface

6: The Bus InterfaceARM720T CORE CPU MANUAL EPSON 6-56.3 Transfer types The ARM720T processor bus interface is pipelined, so the address-class signals

6: The Bus Interface6-6 EPSON ARM720T CORE CPU MANUALFigure 6-4 shows some examples of different transfer types.Figure 6-4 Transfer type examplesIn F

6: The Bus InterfaceARM720T CORE CPU MANUAL EPSON 6-76.4 Address and control signalsThe address and control signals are described in the following sec

6: The Bus Interface6-8 EPSON ARM720T CORE CPU MANUAL6.4.4 HBURST[2:0]HBURST[2:0] indicates the type of burst generated by the ARM720T core, as shown

6: The Bus InterfaceARM720T CORE CPU MANUAL EPSON 6-96.5 Slave transfer response signalsAfter a master has started a transfer, the slave determines ho

CONTENTSARM720T CORE CPU MANUAL EPSON vFigure 9-4 Clock synchronization ...

6: The Bus Interface6-10 EPSON ARM720T CORE CPU MANUAL6.5.2 HRESP[1:0]HRESP[1:0] is used by the slave to show the status of a transfer. The HRESP[1:0]

6: The Bus InterfaceARM720T CORE CPU MANUAL EPSON 6-116.6.2 HRDATA[31:0]The read data bus is driven by the appropriate slave during read transfers. If

6: The Bus Interface6-12 EPSON ARM720T CORE CPU MANUALTable 6-7 shows active byte lanes for big-endian systems.6.7 ArbitrationThe arbitration mechanis

6: The Bus InterfaceARM720T CORE CPU MANUAL EPSON 6-136.8 Bus clockingThere are two clock inputs on the ARM720T processor bus interface.6.8.1 HCLKThe

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7Memory Management Unit

7: Memory Management UnitARM720T CORE CPU MANUAL EPSON 7-17 Memory Management UnitThis chapter describes the Memory Management Unit (MMU). It contains

7: Memory Management Unit7-2 EPSON ARM720T CORE CPU MANUAL7.1.1 Access permissions and domainsFor large and small pages, access permissions are define

7: Memory Management UnitARM720T CORE CPU MANUAL EPSON 7-37.2 MMU program-accessible registersTable 7-1 lists the CP15 registers that are used in conj