Epson S1C6200A Especificaciones Pagina 116
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I-104 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0E7H
0 0 0 EIMEL
R
0
0
0
EIMEL
0 Enable Mask
Interrupt mask register (melody)
R/W
0ECH
0 0 0 IMEL
R
0
0
0
IMEL
0
Interrupt factor flag (melody)
Yes No
0F0H
0F1H
0F2H
MAD3 MAD2 MAD1 MAD0
0 MAD6 MAD5 MAD4
CLKC1 CLKC0 TEMPC MELC
R/W
R
R/W
MAD3
MAD2
MAD1
MAD0
0
0
0
0
0
MAD6
MAD5
MAD4
0
0
0
Melody ROM address (AD6, MSB)
Melody ROM address (AD5)
Melody ROM address (AD4)
CLKC1
CLKC0
TEMPC
MELC
0
0
0
0
CLKC1(0)&CLKC0(0) : melody speed 1
CLKC1(0)&CLKC0(1) : melody speed 8
CLKC1(1)&CLKC0(0) : melody speed 16
CLKC1(1)&CLKC0(1) : melody speed 32
Tempo change control
Melody control ON/OFF
Melody ROM address (AD3)
Melody ROM address (AD2)
Melody ROM address (AD1)
Melody ROM address (AD0, LSB)
High
High
High
High
Low
Low
Low
Low
High
High
High
Low
Low
Low
High
High
High
ON
Low
Low
Low
OFF
R/W
×
×
×
×
0F4H
R12
MO
ENV
R11
R10
FOUT
R/W
MELD
R12
MO
ENV
R11
R10
FOUT
Melody output mask
Output port data (R12)
Inverting melody output
Melody envelope control
Output port data (R11)
Output port data (R10)
Frequency output
Disable
High
–
–
High
High
ON
Enable
Low
–
–
Low
Low
OFF
0
0
–
Hz
0
0
MELD
Control of the
melody generator
Operation of registers for melody control is explained in this
section.
Table 4.11.9 Control bits of melody generator
- S1C62N82 1
- Technical Hardware 7
- CONTENTS 10
- Hardware 11
- INTRODUCTION 13
- CHAPTER 1 13
- Features 14
- EPSON I-3 15
- CHAPTER 1: INTRODUCTION 15
- Core CPU S1C6200A 16
- Pin Layout Diagram 17
- Fig. 1.4.2 18
- Pin assignment 18
- Pin Description 19
- Power Supply 20
- Initial Reset 21
- Table 2.2.1 22
- Input port combinations 22
- Test Pin (TEST) 23
- CPU, ROM, RAM 24
- Fig. 3.2.1 25
- ROM configuration 25
- Memory Map 26
- EPSON I-15 27
- EPSON I-19 31
- EPSON I-21 33
- Oscillation Circuit 34
- OSC3 oscillation 35
- Configuration of 36
- Control of oscillation 37
- Input Ports (K00–K03, K10) 39
- Input comparison 40
- EPSON I-29 41
- Mask option 43
- Control of input ports 44
- EPSON I-35 47
- Control of output 51
- R10 Register 52
- FOUT output 52
- I/O Ports (P00–P03) 53
- Control of I/O port 54
- EPSON I-43 55
- LCD Driver 57
- Frame frequency 58
- Fig. 4.6.5 61
- Segment allocation 61
- Fig. 4.6.6 63
- Clock Timer 65
- Frequency 66
- Control of clock 67
- EPSON I-57 69
- Stopwatch Timer 70
- Count-up pattern 71
- Interrupt function 72
- Control of stopwatch 73
- EPSON I-63 75
- Configuration of SVD 76
- Operation of SVD 78
- Operation of heavy 79
- Control of SVD cir 80
- EPSON I-69 81
- Analog Voltage Comparator 82
- Operation of analog 83
- Control of analog 84
- 4.11 Melody Generator 85
- Fig. 4.11.1 87
- Melody generator 87
- Fig. 4.11.2 88
- Frequency booster 88
- Fig. 4.11.4 90
- Address register 90
- Fig. 4.11.5 91
- Address counters 91
- Table 4.11.1 92
- Dividing ratio 92
- Fig. 4.11.6 92
- Table 4.11.2 93
- Counter setting and tempo 93
- Table 4.11.3 93
- Tempo and switch setting 93
- TS3TS2TS1TS0 94
- EPSON I-83 95
- Table 4.11.5 (b) 97
- Scale ROM data and interval 97
- (without frequency booster) 97
- Data bus 100
- (with external 101
- EPSON I-91 103
- Melody data 104
- Table 4.11.6 105
- Note data and notes 105
- Playing of silent note 107
- Envelope function 108
- Attack signal 109
- R12 pin output 109
- Melody signal 109
- MO pin output 109
- Playing tempo 110
- Table 4.11.8 111
- Playing speed 111
- Playing mode 112
- EPSON I-101 113
- Fig. 4.11.18 114
- Level hold mode 114
- Fig. 4.11.19 115
- Retrigger mode 115
- Control of the 116
- EPSON I-105 117
- Table 4.11.10 118
- EPSON I-107 119
- Interrupt and HALT 120
- Interrupt flag 121
- Interrupt factors 122
- Specific masks and 123
- Interrupt vectors and 124
- Control of interrupt 125
- EPSON I-115 127
- BASIC EXTERNAL WIRING DIA 129
- CHAPTER 5 129
- S1C62L82 130
- S1C62A82 130
- (3) Envelope Driving 131
- (4) Envelope Driving 132
- 6.1 Absolute Maximum Rating 133
- 6.3 DC Characteristics 135
- Analog comparator 137
- EPSON I-131 143
- CHAPTER 7 PACKAGE 145
- CHAPTER 7: PACKAGE 146
- EPSON I-135 147
- CHAPTER 8 PAD LAYOUT 148
- 8.2 Pad Coordinates 149
- Technical Software 151
- Software 155
- CONFIGURATION 157
- Fig. 1.2.1 158
- Configuration of built-in ROM 158
- 1.3 Interrupt Vectors 159
- Data Memory Map 160
- EPSON II-5 161
- CHAPTER 1: CONFIGURATION 161
- EPSON II-9 165
- EPSON II-11 167
- INITIAL RESET 168
- CHAPTER 2 168
- EPSON II-13 169
- CHAPTER 2: INITIAL RESET 169
- Initialize Program Example 170
- Fig. 2.2.1 171
- PERIPHERAL CIRCUITS 172
- CHAPTER 3 172
- Examples of oscilla 173
- Switch the CPU clock to OSC1 174
- Set OSC3 to OFF 174
- Return to parent routine 174
- Input Ports3.2 175
- Control of 176
- Examples of input 177
- Output Ports3.3 178
- Examples of output 179
- Special Use Output Ports3.4 180
- Control of the spe 181
- Example of special 182
- 3.5 I/O Ports 183
- Examples of I/O port 184
- A register 185
- LCD Driver3.6 187
- Control of the LCD 188
- Register 189
- Examples of 190
- LCD driver control 190
- D3 D2 D1 D0 191
- Set address of display memory 193
- Display of underline 193
- Fig. 3.6.7 194
- Example of dot matrix LCD 194
- 3.7 Timer 195
- Control of the timer 196
- Examples of timer 197
- 3.8 Stopwatch Timer 199
- Control of the stop 200
- Examples of stop 201
- SWH3 SWH2 SWH1 SWH0 202
- B register 202
- SWL3 SWL2 SWL1 SWL0 202
- SVD circuit and 203
- Control of the SVD 204
- Example of SVD 204
- Heavy load protec 205
- Examples of heavy 207
- Fig. 3.9.4 209
- Flow chart of operation 209
- 3.10 Analog Comparator 210
- Example of CMP 211
- 3.11 Melody Generator 212
- Address setting 213
- (Addresses 0F0H and 213
- Play mode control 213
- Fig. 3.11.2 214
- Control procedure of 214
- (2) Level hold 215
- Fig. 3.11.4 216
- Fig. 3.11.5 217
- Control procedure of tempo 217
- Fig. 3.11.6 219
- Control procedure of play 219
- Melody interrupt 220
- Melody ROM 220
- Table 3.11.4 221
- Note data 221
- Fig. 3.11.8 221
- Waveform of envelope 221
- Scale ROM 222
- EPSON II-67 223
- EPSON II-69 225
- 3.12 Interrupt and Halt 226
- EPSON II-71 227
- Control of interrupts 229
- Fig. 3.12.1 230
- Fig. 3.12.2 231
- K10 input interrupt circuit 231
- Fig. 3.12.3 232
- Timer interrupt circuit 232
- Fig. 3.12.4 233
- Stopwatch interrupt 233
- EPSON II-79 235
- EPSON II-81 237
- Interrupt 238
- Vector Address 238
- Priority 238
- EPSON II-83 239
- Fig. 3.12.6 240
- Internal interrupt circuit 240
- Examples of interrupt 241
- EPSON II-87 243
- EPSON II-89 245
- EPSON II-91 247
- EPSON II-93 249
- EPSON II-95 251
- Registers specified 253
- EPSON II-99 255
- EPSON II-101 257
- EPSON II-103 259
- Source File Name 260
- Statement (line) 260
- 1 2 3 4 5 6 7 8 261
- APPENDIX F Dividing Table 262
- EPSON II-107 263
- APPENDIX F: DIVIDING TABLE 263
- APPENDIX G RAM Map 264
- EPSON II-109 265
- APPENDIX G: RAM MAP 265
- Epson IS energy savings 267
- First issue November, 1991 268
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