Epson TM-T88II Series Manual de instrucciones Pagina 63

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2-24 Mechanisms and Operation Rev. A
Reset circuit
The reset circuit protects against runaway CPU processing during unstable voltages
immediately after power up, abnormal printing, and other unforeseen operation. Output of the
OUT pin (PIN 6) of the reset IC (Us) is supplied to the CPU (U4) as a RESET input signal (PIN
30). The reset ICC (U2) monitors +5V voltage, and release the CPU reset when voltage rises
above 4.5V, which enable printer operation. The reset IC (U2) C terminal (PIN 5) is connected to
the reset signal (DSR signal or PIN 25 input signal) from the host interface, via DIP switch 2-7 or
2-8. Reset signals can be supplied power to cause reset IC output to become low, which resets
the CPU.
71 PE7 Not used. Open I TTL
72 PE6 Not used. Open O TTL
73 PE5 Not used. Open O TTL
74 PE4 Not used. Open O TTL
75 PE3 Not used. Open O TTL
76 PE2 OTTL
77 PE1 OTTL
78 PE0 OTTL
79 VSS VSS GND terminal I (0V)
80 PF7 Not used. Open O TTL
81 PF6 Not used. Open O TTL
82 PF5 Not used. Open O TTL
83 PF4 Not used. Open O TTL
84 PF3 PF3 Not used. Open O TTL
85 PG4 PG4
86 PG3 PG3
87 PG2 PG2
88 PG1 PG1
89 PG0 PG0
90 VSS VSS GND terminal I (0V)
91 VDD VDD Main power supply terminal (+5) I (+5V)
92 RSCLK RSCLK Thermal head clock signal O TTL
93 RSI RSI Thermal head serial data signal
94 RLT RLT Thermal head latch signal
95 RSTB2 RSTB2 Thermal head strobe signal 2
96 RSTB1 RSTB1 Thermal head strobe signal 1
97 PF2 PF2 Not used. Open O TTL
98 PF1 DKD2 Drawer kick driver signal 2; L: ON O TTL
99 PF0 DKD1 Drawer kick driver signal 1; L: ON O TTL
100 VSS VSS GND terminal I (0V)
Gate array signal assignments and functions (continued)
No. Pin name Signal name Function I/O Level
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