Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario Pagina 10
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1 SUMMARY
2
EPSON
S1C33 FAMILY C33 PE CORE MANUAL
1.2 Summary of Added/Changed Functions of the C33 PE
The functions below have been added to or changed for the C33 PE Core, based on functions of the C33 STD Core
CPU (S1C33000). For details, see the description of each function in subsequent sections of this manual.
1.2.1 Instructions
The C33 PE Core instruction set is compatible with the C33 STD Core CPU, note, however, that some existing
instructions have been function extended or removed and new instructions have been added for high-performance
operations and cost reduction.
Function-extended instructions
The C33 PE Core has the following function-extended instructions. For details, see the description of each
instruction in subsequent sections of this manual.
1. The number of bits shifted by shift/rotate instructions has been increased from 8 to 32.
shift %rd,imm5 * 0–8 bits shift → 0–32 bits shift, shift = srl, sll, sra, sla, rr, rl
shift %rd,%rs 0–8 bits shift → 0–32 bits shift, shift = srl, sll, sra, sla, rr, rl
∗ Although the “shift %rd,imm5” instruction uses two actual instruction codes, they are each counted
as one in the number of instructions shown on the preceding page.
2. The data transfer instructions between a general-purpose register and a special register have been modified
to support newly added special registers.
ld.w %sd,%rs Special register specifiable in %sd added
ld.w %rd,%ss Special register specifiable in %ss added
Added instructions
The instructions added to the C33 PE Core are listed below. For details, see the description of each instruction
in subsequent sections of this manual.
1. Instructions specifically designed to save and restore single or special registers have been added.
push %rs Pushes single register
pop %rd Pops single register
pushs %ss Pushes special registers successively
pops %sd Pops special registers successively
2. Instructions specifically designed for use with the coprocessor interface have been added.
ld.c %rd,imm4 Coprocessor data transfer
ld.c imm4,%rs Coprocessor data transfer
do.c imm6 Coprocessor execution
ld.cf Coprocessor flag transfer
3. Other special instructions have been added.
swaph %rd,%rs Switches between big and little endians
psrset imm5 Sets the PSR bit
psrclr imm5 Clears the PSR bit
jpr %rb Register indirect unconditional relative branch
Instructions removed
In the C33 PE Core, the instructions listed below have been removed from the instruction set of the C33 STD
Core CPU.
div0s Preprocessing for signed step division
div0u Preprocessing for unsigned step division
div1 Step division
div2s Correction of the result of signed step division, 1
div3s Correction of the result of signed step division, 2
mac Multiply-accumulate operation
scan0 Scan bits for 0
scan1 Scan bits for 1
mirror Mirroring
These functions can be realized using the software library provided or by other means.
- S1C33 Family C33 PE 1
- CONTENTS 5
- 1 Summary 9
- 1.2.1 Instructions 10
- 1.2.2 Registers 11
- 2 Registers 12
- Processor Status Register 13
- 2 REGISTERS 14
- EPSON 14
- 2.4 Stack Pointer (SP) 15
- 0xFFFFFFFF 16
- 0x00000000 16
- 0x00060000 18
- 2.9.2 Special Registers 20
- Byte 38-bit data 21
- SSSSSSSS 22
- Example: ld.w %rd,%rs 24
- Example: ld.w %rd,[%rb] 24
- Example: ld.w [%rb],%rs 24
- 4 Address Map 25
- 5 Instruction Set 26
- 5 INSTRUCTION SET 27
- Table 5.1.2 Symbol Meanings 27
- 5.4 Instructions Removed 29
- 5.5.1 Immediate Addressing 30
- Extension of imm6 33
- Extension of sign6 33
- Adding displacement to [%rb] 34
- 00000000 35
- Data + imm26 36
- New address 37
- 5.10 Multiply Instructions 42
- Before execution of pushn 45
- Before execution of push 46
- Before execution of pop 46
- Branch destination address 47
- 5.16 Swap Instructions 53
- 5.17 Other Instructions 54
- 6 Functions 55
- 6.2 Program Execution 56
- 6 FUNCTIONS 57
- Added instructions 59
- 6.3.1 Priority of Exceptions 60
- TTBR[31:10] 61
- Vector code (10 bits) 61
- 6.3.3 Exception Handling 62
- 6.3.4 Reset 62
- 6.3.6 NMI 63
- 6.3.7 Software Exceptions 63
- 6.3.10 ext Exception 64
- 6.4 Power-Down Mode 65
- 6.5 Debug Circuit 66
- 6.6 Coprocessor Interface 67
- 7 Details of Instructions 68
- IE C V Z N 100
- (after execution) 156
- Sign bit 166
- 8 716 1524 23 173
- (in Order of Codes) 177
- Class 4 (1) 179
- Class 4 (2) 179
- Class 5 (1) 179
- Class 5 (2) 179
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