Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario Pagina 122

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7 DETAILS OF INSTRUCTIONS
114
EPSON
S1C33 FAMILY C33 PE CORE MANUAL
ld.uh %rd, %rs
Function
Unsigned halfword data transfer
Standard) rd(15:0)
rs(15:0), rd(31:16) 0
Extension 1) Unusable
Extension 2) Unusable
Code
15 12 11 8 7 4 3 0
1 0 1 0 1 1 0 1
r s r d
0xAD__
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Flag
IE C V Z N
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Mode
Src: Register direct %rs = %r0 to %r15
Dst: Register direct
%rd = %r0 to %r15
CLK
One cycle
Description
(1) Standard
The 16 low-order bits of the rs register are transferred to the rd register after being zero-
extended to 32 bits.
(2) Delayed instruction
This instruction may be executed as a delayed instruction by writing it directly after a branch
instruction with the d bit.
Example
ld.uh %r0,%r1 ; r0 r1(15:0) zero-extended
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