Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario descargar pdf (Pagina 59)

6 FUNCTIONS

S1C33 FAMILY C33 PE CORE MANUAL

EPSON

Added instructions

Table 6.2.2.3 Number of Instruction Execution Cycles and Flag Status (Added Instructions)

Classification

Branch

System control

Coprocessor control

Other

jpr

jpr.d

psrset

psrclr

ld.c

do.c

ld.cf

swaph

push

pop

pushs

pops

%rb

imm5

%rd,imm4

imm4,%rs

imm6

%rd,%rs

%rs

%rd

%ss

%sd

Mnemonic

Remark

Cycle

2–3 (∗3)

2–3 (∗6)

–

↔

–

↔

–

↔

–

↔

–

↔

–

↔

–

↔

–

↔

–

Flag

∗1 Three cycles when the branch conditions are satisfied and the instruction is not a delayed branch instruction

∗2 Zero cycles when lookahead decoding is possible

∗3 When a branch instruction does not involve a delayed branch (not accompanied by the extension “.d”),

a 1-instruction equivalent blank time occurs, as no instructions are executed during a branch; therefore,

apparently +1 cycle.

∗4 +1 cycle when ext is used

∗5 Three cycles when %psr is specified

∗6 Two cycles when %alr is specified or three cycles when %ahr is specified

In the C33 PE Core, no interlock cycle is generated.

1 2 ... 54 55 56 57 58 59 60 61 62 63 64 ... 180 181

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Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario Pagina 59

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