Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario descargar pdf (Pagina 21)

3 DATA FORMATS

S1C33 FAMILY C33 PE CORE MANUAL

EPSON

3 Data Formats

The C33 PE Core can handle data of 8, 16, and 32 bits in length. In this manual, data sizes are expressed as follows:

8-bit data

Byte, B, or b

16-bit data Halfword

, H, or h

32-bit data Word

, W, or w

Data sizes can be selected only in data transfer (load instruction) between memory and a general-purpose register,

and between one general-purpose register and another.

As all internal processing in the processor is performed in 32 bits, in a 16-bit or 8-bit data transfer with a general-

purpose register as the destination, the data is sign- or zero-extended to 32 bits before being loaded into the register.

Whether the data will be sign- or zero-extended is determined by the load instruction used.

In a 16-bit or 8-bit data transfer using a general-purpose register as the source, the data to be transferred is stored in

the high-order halfword or the 1 low-order byte of the source register.

Memory is accessed in little endian format one byte, halfword, or word at a time.

If memory is to be accessed in halfword or word units, the specified base address must be on a halfword boundary

(least significant address bit = 0) or word boundary (2 low-order address bits = 00), respectively. Unless this

condition is satisfied, an address-misaligned exception is generated.

Byte 38-bit data

31 24

Byte 2

23 16

Byte 1

15 8

Byte 0

7 0

Halfword 116-bit data

31 16

Halfword 0

15 0

Word32-bit data

31 0

Figure 3.1 Little Endian Format

The data transfer sizes and types are described below.

3.1 Unsigned 8-Bit Transfer (Register → Register)

Example: ld.ub %rd,%rs

X%rs

31 24

23 16

15 8

Byte

7 0

00000000

31 24 23 16 15 8

Byte

7 0

%rd

00000000

Figure 3.1.1 Unsigned 8-Bit Transfer (Register → Register)

Bits 31–8 in the destination register are zero-extended.

3.2 Signed 8-Bit Transfer (Register → Register)

Example: ld.b %rd,%rs

X%rs

31 24

23 16

15 8 7 0

SSSSSSSS

31 24 23 16 15 8

Byte

7 0

%rd

SSSSSSSS

Byte

Figure 3.2.1 Signed 8-Bit Transfer (Register → Register)

Bits 31–8 in the destination register are sign-extended.

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 180 181

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Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario Pagina 21

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