
7 DETAILS OF INSTRUCTIONS
66
EPSON
S1C33 FAMILY C33 PE CORE MANUAL
and %rd, sign6
Function
Logical AND
Standard) rd
← rd & sign6
Extension 1) rd
← rd & sign19
Extension 2) rd
← rd & sign32
Code
15 12 11 10 9 4 3 0
0 1 1 1 0 0
sign6 r d
0x70__
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Flag
IE C V Z N
– – 0
↔ ↔
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Mode
Src: Immediate data (signed)
Dst: Register direct
%rd = %r0 to %r15
CLK
One cycle
Description
(1) Standard
and
%rd,sign6 ; rd ← rd & sign6
The content of the rd register and the sign-extended 6-bit immediate
sign6 are logically AND’
ed, and the result is loaded into the rd register.
(2) Extension 1
ext
imm13 ; = sign19(18:6)
and
%rd,sign6 ; rd ← rd & sign19, sign6 = sign19(5:0)
The content of the rd register and the sign-extended 19-bit immediate sign19 are logically
AND’ed, and the result is loaded into the rd register.
(3) Extension 2
ext
imm13 ; = sign32(31:19)
ext
imm13 ; = sign32(18:6)
and
%rd,sign6 ; rd ← rd & sign32, sign6 = sign32(5:0)
The content of the rd register and the 32-bit immediate
sign32 are logically AND’ed, and the
result is loaded into the rd register.
(4) Delayed instruction
This instruction may be executed as a delayed instruction by writing it directly after a branch
instruction with the “d” bit. In this case, extension of the immediate by the ext instruction
cannot be performed.
Example
(1) and %r0,0x3e ; r0 = r0 & 0xfffffffe
(2)
ext 0x7ff
and %r1,0x3f ; r1 = r1 & 0x0001ffff
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