Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario Pagina 27
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5 INSTRUCTION SET
S1C33 FAMILY C33 PE CORE MANUAL
EPSON
19
Classification
Data transfer
System control
Immediate extension
Bit manipulation
Other
Function
General-purpose register (byte)
→ general-purpose register (sign-extended)
Memory (byte)
→ general-purpose register (sign-extended)
Postincrement possible
Stack (byte) → general-purpose register (sign-extended)
General-purpose register (byte)
→ memory
Postincrement possible
General-purpose register (byte)
→ stack
General-purpose register (byte)
→ general-purpose register (zero-extended)
Memory (byte)
→ general-purpose register (zero-extended)
Postincrement possible
Stack (byte) → general-purpose register (zero-extended)
General-purpose register (halfword) → general-purpose register (sign-extended)
Memory (halfword) → general-purpose register (sign-extended)
Postincrement possible
Stack (halfword)
→ general-purpose register (sign-extended)
General-purpose register (halfword)
→ memory
Postincrement possible
General-purpose register (halfword)
→ stack
General-purpose register (halfword) → general-purpose register (zero-extended)
Memory (halfword) → general-purpose register (zero-extended)
Postincrement possible
Stack (halfword) → general-purpose register (zero-extended)
General-purpose register (word)
→ general-purpose register
Immediate
→ general-purpose register (sign-extended)
Memory (word)
→ general-purpose register
Postincrement possible
Stack (word)
→ general-purpose register
General-purpose register (word)
→ memory
Postincrement possible
General-purpose register (word) → stack
No operation
HALT
SLEEP
Extend operand in the following instruction
Test a specified bit in memory data
Clear a specified bit in memory data
Set a specified bit in memory data
Invert a specified bit in memory data
Bytewise swap on byte boundary in word
Push general-purpose registers %rs–%r0 onto the stack
Pop data for general-purpose registers %rd–%r0 off the stack
ld.b
ld.ub
ld.h
ld.uh
ld.w
nop
halt
slp
ext
btst
bclr
bset
bnot
swap
pushn
popn
%rd,%rs
%rd,
[%rb]
%rd,[%rb]+
%rd,[%sp+imm6
]
[%rb],%rs
[%rb]+,%rs
[%sp+imm6
],%rs
%rd,%rs
%rd,
[%rb]
%rd,
[%rb]+
%rd,[%sp+imm6
]
%rd,%rs
%rd,
[%rb]
%rd,
[%rb]+
%rd,[%sp+imm6
]
[%rb],%rs
[%rb]+,%rs
[%sp+imm6
],%rs
%rd,%rs
%rd,[%rb]
%rd,[%rb]+
%rd,[%sp+imm6
]
%rd,%rs
%rd,sign6
%rd,
[%rb]
%rd,
[%rb]+
%rd,[%sp+imm6
]
[%rb],%rs
[%rb]+,%rs
[%sp+imm6],%rs
imm13
[%rb],imm3
[%rb],imm3
[%rb],imm3
[%rb],imm3
%rd,%rs
%rs
%rd
Mnemonic
The symbols in the above table each have the meanings specified below.
Table 5.1.2 Symbol Meanings
Symbol
%rs
%rd
%ss
%sd
[%rb]
[%rb]+
%sp
imm2,imm4,imm3,
imm5,imm6,imm10,
imm13
sign6,sign8
Description
General-purpose register, source
General-purpose register, destination
Special register, source
Special register, destination
General-purpose register, indirect addressing
General-purpose register, indirect addressing with postincrement
Stack pointer
Unsigned immediate (numerals indicating bit length)
However, numerals in shift instructions indicate the number of bits
shifted, while those in bit manipulation indicate bit positions.
Signed immediate (numerals indicating bit length)
- S1C33 Family C33 PE 1
- CONTENTS 5
- 1 Summary 9
- 1.2.1 Instructions 10
- 1.2.2 Registers 11
- 2 Registers 12
- Processor Status Register 13
- 2 REGISTERS 14
- EPSON 14
- 2.4 Stack Pointer (SP) 15
- 0xFFFFFFFF 16
- 0x00000000 16
- 0x00060000 18
- 2.9.2 Special Registers 20
- Byte 38-bit data 21
- SSSSSSSS 22
- Example: ld.w %rd,%rs 24
- Example: ld.w %rd,[%rb] 24
- Example: ld.w [%rb],%rs 24
- 4 Address Map 25
- 5 Instruction Set 26
- 5 INSTRUCTION SET 27
- Table 5.1.2 Symbol Meanings 27
- 5.4 Instructions Removed 29
- 5.5.1 Immediate Addressing 30
- Extension of imm6 33
- Extension of sign6 33
- Adding displacement to [%rb] 34
- 00000000 35
- Data + imm26 36
- New address 37
- 5.10 Multiply Instructions 42
- Before execution of pushn 45
- Before execution of push 46
- Before execution of pop 46
- Branch destination address 47
- 5.16 Swap Instructions 53
- 5.17 Other Instructions 54
- 6 Functions 55
- 6.2 Program Execution 56
- 6 FUNCTIONS 57
- Added instructions 59
- 6.3.1 Priority of Exceptions 60
- TTBR[31:10] 61
- Vector code (10 bits) 61
- 6.3.3 Exception Handling 62
- 6.3.4 Reset 62
- 6.3.6 NMI 63
- 6.3.7 Software Exceptions 63
- 6.3.10 ext Exception 64
- 6.4 Power-Down Mode 65
- 6.5 Debug Circuit 66
- 6.6 Coprocessor Interface 67
- 7 Details of Instructions 68
- IE C V Z N 100
- (after execution) 156
- Sign bit 166
- 8 716 1524 23 173
- (in Order of Codes) 177
- Class 4 (1) 179
- Class 4 (2) 179
- Class 5 (1) 179
- Class 5 (2) 179
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