Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario descargar pdf (Pagina 65)

6 FUNCTIONS

S1C33 FAMILY C33 PE CORE MANUAL

EPSON

6.4 Power-Down Mode

The C33 PE Core supports two power-down modes: HALT and SLEEP modes.

HALT mode

Program execution is halted at the same time that the C33 PE Core executes the halt instruction, and the

processor enters HALT mode.

HALT mode commonly turns off only the C33 PE Core operation, note, however that modules to be turned off

depend on the implementation of the clock control circuit outside the core. Refer to the technical manual of

each model for details.

SLEEP mode

Program execution is halted at the same time the C33 PE Core executes the slp instruction, and the processor

enters SLEEP mode.

SLEEP mode commonly turns off the C33 PE Core and on-chip peripheral circuit operations, thereby it

significantly reduces the current consumption in comparison to the HALT mode. However, modules to be

turned off depend on the implementation of the clock control circuit outside the core. Refer to the technical

manual of each model for details.

Canceling HALT or SLEEP mode

Initial reset is one cause that can be bring the processor out of HALT or SLEEP mode. Other causes depend on

the implementation of the clock control circuit outside the C33 PE Core.

Initial reset, maskable external interrupts, NMI, and debug exceptions are commonly used for canceling HALT

and SLEEP modes.

The interrupt enable/disable status set in the processor does not affect the cancellation of HALT or SLEEP

modes even if an interrupt signal is used as the cancellation. In other words, interrupt signals are able to cancel

HALT and SLEEP modes even if the IE flag in PSR or the interrupt enable bits in the interrupt controller

(depending on the implementation) are set to disable interrupts.

When the processor is taken out of HALT or SLEEP mode using an interrupt that has been enabled (by the

interrupt controller and IE flag), the corresponding interrupt handler routine is executed. Therefore, when the

interrupt handler routine is terminated by the

reti instruction, the processor returns to the instruction next to

halt or slp.

When the interrupt has been disabled, the processor restarts the program from the instruction next to

halt or

slp after the processor is taken out of HALT or SLEEP mode.

1 2 ... 60 61 62 63 64 65 66 67 68 69 70 ... 180 181

Sin comentarios

Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario Pagina 65