Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario descargar pdf (Pagina 61)

6 FUNCTIONS

S1C33 FAMILY C33 PE CORE MANUAL

EPSON

6.3.2 Vector Table

Vector table in the C33 PE Core

The table below lists the exceptions and interrupts for which the vector table is referenced during exception

handling. The priorities of these exceptions and interrupts are managed by the interrupt controller (ITC).

Table 6.3.2.1 Vector List

Exception

Reset

reserved

ext exception

Undefined instruction exception

reserved

Address misaligned exception

NMI

reserved

Software exception 0

Software exception 1

Software exception 2

Software exception 3

Maskable external interrupt 0

Maskable external interrupt 239

Vector No.

4–5

8–11

255

Synchronous/

asynchronous

Asynchronous

–

Synchronous

–

Synchronous

Asynchronous

–

Synchronous

Asynchronous

Classification

Interrupt

–

Exception

–

Exception

Interrupt

–

Exception

Interrupt

Vector address

TTBR + 0x00

–

TTBR + 0x08

TTBR + 0x0C

–

TTBR + 0x18

TTBR + 0x1C

–

TTBR + 0x30

TTBR + 0x34

TTBR + 0x38

TTBR + 0x3C

TTBR + 0x40

TTBR + 0x3FC

The sources of exceptions in the C33 PE Core are shown in Table 6.3.2.1.

The Synchronous/Asynchronous column of the table indicates whether the relevant exception is generated

synchronously or asynchronously with the program execution. Those that occur synchronously with the

program execution are classified as “exceptions,” and those that occur asynchronously are classified as

“interrupts.” In this manual, the internal processing performed by the processor for interrupts and exceptions

that occurred is referred to collectively as “exception handling.”

The vector address is one that contains a vector (or the jump address) for the user’s exception handler routine

that is provided for each exception and is executed when the relevant exception occurs. Because an address

value is stored, each vector address is located at a word boundary. The memory area in which these vectors are

stored is referred to as the “vector table.” The “TTBR” in the Vector Address column represents the base (start)

address of the vector table.

In the C33 PE Core, the TTBR is provided as a special register, and because this register can be written to in the

software, the vector table can be mapped into any desired area in the RAM.

TTBR (Trap Table Base Register)

00000000000000000000000000000100

091031

Fixed

(R only)

TTBR

1K-byte boundary address

(R/W)

The initial value of the TTBR, or the value to which the TTBR is initialized when cold reset, is “0x00C00000.”

Referenced vector-table addresses

When an exception occurs, the vector table is referenced from the TTBR value and a 10-bit vector code that

is assigned to each exception source. As only bits 31–10 in the TTBR are referenced, the vector table must be

located in a 1K-byte boundary RAM area.

TTBR[31:10]

Vector code (10 bits)

Vector code is generated by the processor.

1 2 ... 56 57 58 59 60 61 62 63 64 65 66 ... 180 181

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