Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario Pagina 86

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7 DETAILS OF INSTRUCTIONS
78
EPSON
S1C33 FAMILY C33 PE CORE MANUAL
halt
Function
HALT
Standard) Sets the processor to HALT mode
Extension 1) Unusable
Extension 2) Unusable
Code
15 12 11 8 7 4 3 0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
0x0080
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Flag
IE C V Z N
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Mode
CLK
Five cycles
Description
Sets the processor to HALT mode for power saving.
Program execution is halted at the same time that the C33 PE Core executes the
halt instruction,
and the processor enters HALT mode.
HALT mode commonly turns off only the C33 PE Core operation, note, however that modules to be
turned off depend on the implementation of the clock control circuit outside the core.
Initial reset is one cause that can bring the processor out of HALT mode. Other causes depend on
the implementation of the clock control circuit outside the C33 PE Core.
Initial reset, maskable external interrupts, NMI, and debug exceptions are commonly used for
canceling HALT mode.
The interrupt enable/disable status set in the processor does not affect the cancellation of HALT
mode even if an interrupt signal is used as the cancellation. In other words, interrupt signals are
able to cancel HALT mode even if the IE flag in PSR or the interrupt enable bits in the interrupt
controller (depending on the implementation) are set to disable interrupts.
When the processor is taken out of HALT mode using an interrupt that has been enabled (by the
interrupt controller and IE flag), the corresponding interrupt handler routine is executed. Therefore,
when the interrupt handler routine is terminated by the
reti instruction, the processor returns to
the instruction next to
halt.
When the interrupt has been disabled, the processor restarts the program from the instruction next
to halt after the processor is taken out of HALT mode.
Refer to the technical manual of each model for details of HALT mode.
Example
halt ; Sets the processor in HALT mode.
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