Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario Pagina 5
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CONTENTS
S1C33 FAMILY C33 PE CORE MANUAL
EPSON
i
– Contents –
1 Summary ........................................................................................................................
1
1.1 Features ............................................................................................................................ 1
1.2 Summary of Added/Changed Functions of the C33 PE .................................................... 2
1.2.1 Instructions ......................................................................................................... 2
1.2.2 Registers .............................................................................................................
3
1.2.3 Address Space and Other ..................................................................................
3
2 Registers ........................................................................................................................ 4
2.1 General-Purpose Registers (R0–R15) .............................................................................. 4
2.2 Program Counter (PC) ...................................................................................................... 4
2.3 Processor Status Register (PSR) ...................................................................................... 5
2.4 Stack Pointer (SP) ............................................................................................................. 7
2.4.1 About the Stack Area .......................................................................................... 7
2.4.2 SP Operation during Execution of
Push
-Related Instructions ............................ 7
2.4.3 SP Operation during Execution of
Pop
-Related Instructions .............................. 8
2.4.4 SP Operation during Execution of a
Call
Instruction ........................................ 8
2.4.5 SP Operation when an Interrupt or Exception Occurs ........................................
9
2.5 Trap Table Base Register (TTBR) .....................................................................................
10
2.6 Arithmetic Operation Registers (ALR and AHR) .............................................................. 10
2.7 Processor Identification Register (IDIR) ........................................................................... 10
2.8 Debug Base Register (DBBR) .......................................................................................... 10
2.9 Register Notation and Register Numbers ........................................................................ 11
2.9.1 General-Purpose Registers ............................................................................... 11
2.9.2 Special Registers ...............................................................................................
12
3 Data Formats ................................................................................................................. 13
3.1 Unsigned 8-Bit Transfer (Register → Register) ................................................................ 13
3.2 Signed 8-Bit Transfer (Register → Register) .................................................................... 13
3.3 Unsigned 8-Bit Transfer (Memory → Register) ................................................................. 14
3.4 Signed 8-Bit Transfer (Memory → Register) ..................................................................... 14
3.5 8-Bit Transfer (Register → Memory) ................................................................................. 14
3.6 Unsigned 16-Bit Transfer (Register → Register) .............................................................. 14
3.7 Signed 16-Bit Transfer (Register → Register) .................................................................. 15
3.8 Unsigned 16-Bit Transfer (Memory → Register) ............................................................... 15
3.9 Signed 16-Bit Transfer (Memory → Register) ................................................................... 15
3.10 16-Bit Transfer (Register → Memory) ............................................................................. 15
3.11 32-Bit Transfer (Register → Register) ............................................................................ 16
3.12 32-Bit Transfer (Memory → Register) ............................................................................. 16
3.13 32-Bit Transfer (Register → Memory) ............................................................................. 16
4 Address Map ................................................................................................................. 17
5 Instruction Set ..............................................................................................................
18
5.1 S1C33-Series-Compatible Instructions ............................................................................ 18
5.2 Function Extended Instructions ........................................................................................ 20
5.3 Instructions Added to the C33 PE Core ........................................................................... 21
5.4 Instructions Removed ...................................................................................................... 21
- S1C33 Family C33 PE 1
- CONTENTS 5
- 1 Summary 9
- 1.2.1 Instructions 10
- 1.2.2 Registers 11
- 2 Registers 12
- Processor Status Register 13
- 2 REGISTERS 14
- EPSON 14
- 2.4 Stack Pointer (SP) 15
- 0xFFFFFFFF 16
- 0x00000000 16
- 0x00060000 18
- 2.9.2 Special Registers 20
- Byte 38-bit data 21
- SSSSSSSS 22
- Example: ld.w %rd,%rs 24
- Example: ld.w %rd,[%rb] 24
- Example: ld.w [%rb],%rs 24
- 4 Address Map 25
- 5 Instruction Set 26
- 5 INSTRUCTION SET 27
- Table 5.1.2 Symbol Meanings 27
- 5.4 Instructions Removed 29
- 5.5.1 Immediate Addressing 30
- Extension of imm6 33
- Extension of sign6 33
- Adding displacement to [%rb] 34
- 00000000 35
- Data + imm26 36
- New address 37
- 5.10 Multiply Instructions 42
- Before execution of pushn 45
- Before execution of push 46
- Before execution of pop 46
- Branch destination address 47
- 5.16 Swap Instructions 53
- 5.17 Other Instructions 54
- 6 Functions 55
- 6.2 Program Execution 56
- 6 FUNCTIONS 57
- Added instructions 59
- 6.3.1 Priority of Exceptions 60
- TTBR[31:10] 61
- Vector code (10 bits) 61
- 6.3.3 Exception Handling 62
- 6.3.4 Reset 62
- 6.3.6 NMI 63
- 6.3.7 Software Exceptions 63
- 6.3.10 ext Exception 64
- 6.4 Power-Down Mode 65
- 6.5 Debug Circuit 66
- 6.6 Coprocessor Interface 67
- 7 Details of Instructions 68
- IE C V Z N 100
- (after execution) 156
- Sign bit 166
- 8 716 1524 23 173
- (in Order of Codes) 177
- Class 4 (1) 179
- Class 4 (2) 179
- Class 5 (1) 179
- Class 5 (2) 179
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