Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario Pagina 45
- Pagina / 181
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
5 INSTRUCTION SET
S1C33 FAMILY C33 PE CORE MANUAL
EPSON
37
5.13 Push and Pop Instructions
The push and pop instructions are provided to temporarily save the contents of general-purpose or special registers
to the stack, and to restore the saved register data from the stack.
Push instructions
pushn %rs
push
%rs
pushs
%ss
The pushn instruction saves a range of general-purpose registers from rs to R0 to the stack successively. The
push instruction saves the general-purpose register specified by rs to the stack singly. The pushs instruction
saves the special registers (ALR only or AHR and ALR).
Pop instructions
popn %rd
pop
%rd
pops
%sd
The popn instruction restores the saved data from the stack to the general-purpose registers R0 to rd successively.
The pop instruction restores the saved data from the stack to the general-purpose register specified by rd singly.
The pops instruction restores the saved data from the stack to the special registers (ALR only or ALR and AHR).
The push and pop instructions must have the same register specification in pairs. These instructions alter the
SP depending on the number of pieces of data that are saved and restored. Because in addition to the push/pop
instructions, load instructions are available for register indirect addressing with displacement ([%sp+imm6
])
where the SP is the base address, individual store/load operations on each register can be performed with respect to
the SP. In this case, however, the SP is not altered.
A specific register number is assigned to each register (refer to Chapter 2, “Registers”). When general-purpose or
special registers are successively pushed, their data is saved to the stack in descending order of register numbers
beginning with the one specified by rs or ss. In successive pop operations, conversely, the register data is restored in
ascending order from R0 or ALR up to the specified register.
Differences from the C33 STD Core CPU
• General-purpose-register single push/pop instructions have been added.
push %rs pop %rd
• Special-register successive push/pop instructions have been added.
pushs %ss pops %sd
Example 1:
pushn %r15 Push all general-purpose registers onto the stack
popn %r15 Pop all general-purpose registers off the stack
31 0
Before execution of pushn
low address
31 0
After execution of pushn
r15
r14
r13
r12
:
:
r1
r0
low address
SP
SP
The stack pointer is updated before the register data is pushed onto the stack.
SP = SP - 4, rs → [SP]
Figure 5.13.1 Successive Push of General-Purpose Registers
- S1C33 Family C33 PE 1
- CONTENTS 5
- 1 Summary 9
- 1.2.1 Instructions 10
- 1.2.2 Registers 11
- 2 Registers 12
- Processor Status Register 13
- 2 REGISTERS 14
- EPSON 14
- 2.4 Stack Pointer (SP) 15
- 0xFFFFFFFF 16
- 0x00000000 16
- 0x00060000 18
- 2.9.2 Special Registers 20
- Byte 38-bit data 21
- SSSSSSSS 22
- Example: ld.w %rd,%rs 24
- Example: ld.w %rd,[%rb] 24
- Example: ld.w [%rb],%rs 24
- 4 Address Map 25
- 5 Instruction Set 26
- 5 INSTRUCTION SET 27
- Table 5.1.2 Symbol Meanings 27
- 5.4 Instructions Removed 29
- 5.5.1 Immediate Addressing 30
- Extension of imm6 33
- Extension of sign6 33
- Adding displacement to [%rb] 34
- 00000000 35
- Data + imm26 36
- New address 37
- 5.10 Multiply Instructions 42
- Before execution of pushn 45
- Before execution of push 46
- Before execution of pop 46
- Branch destination address 47
- 5.16 Swap Instructions 53
- 5.17 Other Instructions 54
- 6 Functions 55
- 6.2 Program Execution 56
- 6 FUNCTIONS 57
- Added instructions 59
- 6.3.1 Priority of Exceptions 60
- TTBR[31:10] 61
- Vector code (10 bits) 61
- 6.3.3 Exception Handling 62
- 6.3.4 Reset 62
- 6.3.6 NMI 63
- 6.3.7 Software Exceptions 63
- 6.3.10 ext Exception 64
- 6.4 Power-Down Mode 65
- 6.5 Debug Circuit 66
- 6.6 Coprocessor Interface 67
- 7 Details of Instructions 68
- IE C V Z N 100
- (after execution) 156
- Sign bit 166
- 8 716 1524 23 173
- (in Order of Codes) 177
- Class 4 (1) 179
- Class 4 (2) 179
- Class 5 (1) 179
- Class 5 (2) 179
Relacionado con productos y manuales para Barebones Pc / Estación De Trabajo Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03
(128 paginas)© 2020, manymanuals.es. Todos los derechos reservados | 0.115 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales