Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario descargar pdf (Pagina 66)

6 FUNCTIONS

EPSON

S1C33 FAMILY C33 PE CORE MANUAL

6.5 Debug Circuit

The C33 PE Core has a debug circuit to assist in software development by the user.

The debug circuit provides the following functions:

• Instruction break

A debug exception is generated before the set instruction address is executed. An instruction break can be set at

three addresses.

• Data break

A debug exception is generated when the set address is accessed for read or write. A data break can be set at

only one address.

• Single step

A debug exception is generated every instruction executed.

• Forcible break

A debug exception is generated by an external input signal.

• Software break

A debug exception is generated when the

brk instruction is executed.

• PC trace

The status of instruction execution by the processor is traced.

When a debug exception occurs, the processor performs the following processing:

(1) Suspends the instruction currently being executed.

A debug exception is generated at the end of the E stage of the currently executed instruction, and is accepted at

the next rise of the system clock.

(2) Saves the contents of the PC and R0, in that order, to the addresses specified below.

→ 0x00060008

→ 0x0006000C

(3) Loads the debug exception vector located at the address 0x00060000 to PC and branches to the debug exception

handler routine.

In the exception handler routine, the

retd instruction should be executed at the end of processing to return to the

suspended instruction. When returning from the exception by the

retd instruction, the processor restores the saved

data in order of the R0 and the PC.

Neither hardware interrupts nor NMI interrupts are accepted during a debug exception.

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Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario Pagina 66