Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario descargar pdf (Pagina 107)

7 DETAILS OF INSTRUCTIONS

S1C33 FAMILY C33 PE CORE MANUAL

EPSON

ld.b [%sp + imm6], %rs

Function

Signed byte data transfer

Standard) B[sp +

imm6] ← rs(7:0)

Extension 1) B[sp +

imm19] ← rs(7:0)

Extension 2) B[sp +

imm32] ← rs(7:0)

Code

15 12 11 10 9 4 3 0

0 1 0 1 0 1

imm6 r s

0x54__

Flag

IE C V Z N

– – – – –

Mode

Src: Register direct %rs = %r0 to %r15

Dst: Register indirect with displacement

CLK

Two cycle

Description

(1) Standard

ld.b [%sp +

imm6],%rs ; memory address = sp + imm6

The 8 low-order bits of the rs register are transferred to the specified memory location. The

content of the current SP with the 6-bit immediate

imm6 added as displacement comprises the

memory address to be accessed.

(2) Extension 1

ext

imm13 ; = imm19(18:6)

ld.b [%sp +

imm6],%rs ; memory address = sp + imm19,

;

imm6 = imm19(5:0)

The

ext instruction extends the displacement to a 19-bit quantity. As a result, The 8 low-order

bits of the rs register are transferred to the address indicated by the content of the SP with the

19-bit immediate

imm19 added.

(3) Extension 2

ext

imm13 ; = imm32(31:19)

ext

imm13 ; = imm32(18:6)

ld.b [%sp +

imm6],%rs ; memory address = sp + imm32,

;

imm6 = imm32(5:0)

The two

ext instructions extend the displacement to a 32-bit quantity. As a result, The 8 low-

order bits of the rs register are transferred to the address indicated by the content of the SP with

the 32-bit immediate

imm32 added.

Example

ext 0x1

ld.b [%sp + 0x1],%r0 ; B[sp + 0x41]

← 8 low-order bits of r0

1 2 ... 102 103 104 105 106 107 108 109 110 111 112 ... 180 181

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Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manual de usuario Pagina 107

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